The present invention relates to a semiconductor memory including a redundancy circuit for relieving a defective memory cell.
In general, a semiconductor memory has a redundancy circuit for improving the yield of a product. When a defective memory cell exists within a memory cell array (a normal cell array), the redundancy circuit has a function of replacing this defective memory cell with a redundancy memory cell within a spare memory cell array.
At present, it is most general that a redundancy circuit employs a system of replacing a defective memory cell with a redundancy memory cell in a relief unit (replacement unit). The relief unit is a set of memory cells that are replaced at the same time when a defective memory cell is replaced with a redundancy memory cell. Generally, the relief unit is set in either memory cells that are connected to one or a plurality of word lines (row unit), or in memory cells that are connected to one or a plurality of pairs of bit lines (column unit).
When memory cells connected to a plurality of word lines (a plurality of rows) are set as a relief unit, for example, these plurality of word lines are connected to one row decoder, and a defective memory cell is replaced with a redundancy memory cell in a row decoder unit. Further, when memory cells connected to a plurality of pairs of bit lines (a plurality of columns) are set as a relief unit, for example, the plurality of pairs of bit lines are connected to one pair of I/O (Input/Output) lines, and a defective memory cell is replaced with a redundancy memory cell in a unit of the pair of I/O lines.
Further, in the case of a semiconductor memory structured by a plurality of banks that can be accessed substantially simultaneously, one bank (a memory cell array having a constant memory capacity) is set as a relief block unit. The relief block unit is a range in which a replacement in relief unit is effective. In other words, in this case, a defective memory cell is replaced with a redundancy memory cell in each relief unit within one relief block unit. More specifically, a defective memory cell within one bank can be replaced with only a redundancy memory cell within this bank, and the defective memory cell cannot be replaced with a redundancy memory cell within other banks.
In order to replace a defective memory cell with a redundancy memory cell in each relief unit, it is necessary to register in advance an address (a fail address) for specifying a relief unit having a defective memory cell in an address registration memory (for example, a fuse set). Further, it is also necessary to make a decision as to whether or not an external address or an internal address coincides with this fail address at the time of operating the semiconductor memory.
Accordingly, each of the plurality of banks within the semiconductor memory (a memory chip) has address registration memories (fail address memories) by the number equal to that of the relief units. The fail address memories are structured by nonvolatile memories. At present, a fuse is mainly used for the nonvolatile memory. A fail address memory structured by this fuse is called a fuse set.
Relief units and fuse sets are disposed at a ratio of one to one within one bank. In other words, the number of fuse sets within one bank is equal to the number of relief units in this bank.
A fuse set includes a plurality of fuse elements for storing fail addresses. One fuse element can store one bit data depending on whether this fuse element is to be disconnected or not. Accordingly, an N-bit fail address can be stored in N fuse elements.
A structure of the fuse set is simple, and the system for storing fail addresses in a fuse set is most widely employed at present.
FIG. 1 shows a main portion of a semiconductor memory having fuse sets.
In the present example, the semiconductor memory has a plurality of banks that can be accessed substantially simultaneously. One bank forms a relief block unit and one row decoder forms a relief unit.
A memory cell array is structured by eight sub-arrays 10. One sub-array 10 is disposed within one bank BANKi (i=0, 1, . . . 7). In this case, eight banks BANK0, BANK1, . . . BANK7 are adjacently disposed in a column direction, for example. Each BANKi (i=0, 1, . . . 7) includes a normal cell array 11, a spare cell array 12, a row decoder 13, a fixed spare row decoder 14, and a fixed fuse set 15.
The normal cell array 11 has a memory capacity of 512 kilobits, for example. On the normal cell array 11, there are disposed 512 word lines 16 and 1,024 pairs of bit lines. In the present example, the number of the row decoders 13 is set to 128, and four word lines 16 are connected to one row decoder.
The spare cell array 12 has a memory capacity of sixteen kilobits, for example. On the spare memory cell array 12, there are disposed sixteen spare word lines 17 and 1,024 pairs of bit lines. The number of the fixed spare row decoders 14 is set to four. The four spare word lines 17 are connected to one fixed spare row decoder.
A column decoder 19 is disposed adjacent to the bank BANK7 positioned at the last end of the eight banks BANK0, BANK1, . . . BANK7. A column select line CSL 18 is common to the eight banks BANK0, BANK1, . . . BANK7, and is disposed above the eight banks BANK0, BANK1, . . . BANK7. The column select line 18 extends to the BANK0 side from the column decoder 19.
In the present example, one bank is set as a relief block unit, one row decoder (four word lines) is set as a relief unit, and four fixed spare row decoders are disposed within one bank. Therefore, it is possible to replace maximum four row decoders with fixed spare row decoders within one bank.
In other words, when a defective memory cell is included within the normal cell array 11, and also when four or less row decoders out of the 128 row decoders are connected to the defective memory cell, it is possible to replace these defective row decoders with the fixed spare row decoders. As a result, a fraction of defective semiconductor memories can be decreased, and the yield of the products (productivity) can be improved.
Within each bank BANKi (i=0, 1, . . . 7), four fixed fuse sets 15 are provided corresponding to four fixed spare row decoders 14. Each fixed fuse set can store one fail address.
An input address (an external address or an internal address) is input to each fixed fuse set. When the input addresses disagree with the fail addresses in all the fixed fuse sets, for example, the row decoders 13 become active (DISABLE F=xe2x80x9c1xe2x80x9d), and all the fixed spare row decoders 14 become inactive.
Further, when the input address coincides with the fail address in at least one of the fixed fuse sets, the row decoder 13 becomes inactive (DISABLE F=xe2x80x9c0xe2x80x9d), and the fixed spare row decoder corresponding to the at least one of the fixed fuse sets becomes active.
FIG. 2 shows an example of a fixed fuse set within a bank.
In the present example, the four fixed spare row decoders in FIG. 1 correspond to the four fixed fuse sets 15. Accordingly, when the semiconductor memory is structured by eight banks as shown in the example of FIG. 1, the fixed spare row decoders and the fixed fuse sets are provided by thirty-two (=4xc3x978) within the semiconductor memory (memory chip).
When there exist 128 (=27) row decoders within one bank as shown in the example of FIG. 1, seven-bit address signals A0, A1, . . . A6 are necessary in order to specify one of the 128 row decoders. Therefore, in order to store a fail address, at least seven fuse units (fuse elements) 20 are necessary.
In the present example, one fuse unit (fuse element) 20xe2x80x2 is provided as an enable fuse unit for determining whether the fixed fuse set 15 is to be used or not. Accordingly, within one fixed fuse set 15F, the fuse units 20 and 20xe2x80x2 are provided by eight in total.
One fuse unit is structured by a p-channel MOS transistor Qp, an n-channel MOS transistor Qn, and a fuse element FUSE, as shown in FIG. 3. An output signal of the fuse unit is xe2x80x9c1xe2x80x9d when the fuse element FUSE is being disconnected, and is xe2x80x9c0xe2x80x9d when the fuse element FUSE is not being disconnected.
Output signals of the seven fuse units 20 for storing a fail address are input to comparators 22 within a fail address coincidence detector 21. The comparators 22 compare the row addresses A0, A1, . . . A6 with the output signals (fail addresses) of the fuse units 20 respectively. The comparators 22 are structured by exclusive NOR circuits, for example. They output xe2x80x9c1xe2x80x9d when the input addresses coincide with the fail addresses.
Output signals of the comparators 22 and an output signal of the fuse unit 20xe2x80x2 are input to an AND circuit (a fail address coincidence detector) 23. The output signal of the fuse unit (enable fuse) 20xe2x80x2 is set to xe2x80x9c1xe2x80x9d when the fixed fuse set 15 including this fuse unit 20xe2x80x2 is used. The output signal of the fuse unit (enable fuse) 20xe2x80x2 is being set to xe2x80x9c0xe2x80x9d when the fixed fuse set 15 including this fuse unit 20xe2x80x2 is not used.
Accordingly, when the fixed fuse set 15 is used and also when the input address coincides with the fail address, the output signal of the AND circuit (fail address coincidence detector) 23 becomes xe2x80x9c1xe2x80x9d, so that the fixed spare row decoder is activated. In this case, an output signal DISABLE F of an NOR circuit 24 becomes xe2x80x9c0xe2x80x9d, and the row decoder is inactivated. When all the outputs of the four fixed fuse sets 15 are xe2x80x9c0xe2x80x9d, the output signal DISABLE F of the NOR circuit 24 becomes xe2x80x9c1xe2x80x9d, so that the row decoder is activated.
FIG. 4 shows an example of sub-arrays within a bank and their surroundings.
A sense amplifier 25 and a column select switch 26 are disposed within each bank. A pair of bit lines BL and bBL are connected to the sense amplifier 25. In the present example, the pair of bit lines BL and bBL are connected to only one side of the sense amplifier 25. However, the pair of bit lines BL and bBL can also be connected to both sides of the sense amplifier 25.
Memory cells MC are connected to each word line WL, and spare cells (redundancy memory cells) SC are connected to each spare word line SWL. The pair of bit lines BL and bBL are connected to a pair of data lines (a pair of DQ lines) DQ and bDQ through the sense amplifier 25 and the column select switch 26.
The column select lines CSL are connected to the column select switches 26, and the column select lines CSL are provided in common to the plurality of banks as shown by a reference number 18 in FIG. 1. Column address signals are decoded by column decoders, and decoded results are transmitted to the column select switches 26 through the column select lines CSL.
Next, a relationship between the number of fixed fuse sets (fuse elements) within the semiconductor memory (memory chip) and the number of relief units that can be relieved by the fixed fuse sets will be examined.
In the present example, there will be explained about a semiconductor memory having a plurality of banks that can be accessed substantially simultaneously. It is assumed that one bank forms a relief block unit and that 2M (M is a natural number) relief block units are disposed within one semiconductor memory. Further, it is also assumed that 2N relief units (for example, row decoders) assigned by N-bit addresses (N is a natural number) are disposed within one relief block unit and that S (S is a natural number) redundancy relief units (for example, fixed spare row decoders) are disposed within one relief block unit.
The number of fuses within one relief block unit will be examined.
When one of the 2N relief units is a fail, for example, it is necessary to replace this one fail relief unit with one of the S redundancy relief units. The number of fuses necessary for specifying this replacement becomes (N+1) which is a total of one enable fuse for determining whether a fuse set is to be used or not and N fuses for storing the N-bit addresses (fail addresses).
Accordingly, (N+1) fuses are disposed within one fuse set for storing the redundancy replacement data.
Further, as the redundancy relief units exist by S, it is necessary to provide S fuse sets corresponding to these redundancy relief units. As a result, (N+1)xc3x97S fuses in total are disposed within one relief block unit.
Further, as the relief block units are disposed by 2M within the semiconductor memory (chip memory), redundancy fuses are provided by (N+1)xc3x97Sxc3x972M in total within the semiconductor memory.
In the semiconductor memory having the above-described structure, it is possible to replace at least one defective memory cell within each one of the S relief units within one relief block unit. In other words, when the number of the relief units including a defective memory cell is not more than S within one relief block unit, it is possible to relieve the semiconductor memory. On the other hand, when the number of the relief units including a defective memory cell exceeds S, it is not possible to relieve the semiconductor memory.
Accordingly, in a semiconductor memory (memory chip), it is possible to replace defective memory cells with redundancy memory cells by using a redundancy circuit, when the number of the relief units including the defective memory cells is not more than Sxc3x972M. However, within one relief block unit, the number of the relief units including the defective memory cells needs to be S or less.
The above can be summarized as follows.
(1) Total number of redundancy fuses within the chip: (N+1)xc3x97Sxc3x972M 
(2) Total number of redundancy relief units within the chip: Sxc3x972M 
(3) Total number of fuse sets within the chip Sxc3x972M 
(4) Total number of relief units that can be replaced within the chip: Sxc3x972M 
(However, a maximum number of relief units that can be replaced within the relief unit block is S.)
(5) Total number of relief block units within the chip: 2M 
In the mean time, in recent years, it has become most popular that the semiconductor memories having a plurality of banks are used in which the banks can be activated simultaneously and each can be read or written.
In order to improve the yield of a product, it is necessary to improve the relief efficiency of the semiconductor memories. The improvement in the relief efficiency of the semiconductor memories can be achieved by increasing the number of redundancy relief units within each bank (each relief block unit).
However, when the number of relief units is increased, the number of fuse sets provided corresponding to these relief units increases. Thus, the area of the redundancy circuit within the chip increases. As a result, there arises a problem that the area efficiency within the chip is lowered and the chip size increases when a semiconductor memory circuit (excluding the redundancy circuit) is disposed. Particularly, when a statistical distribution of defective memory cells within the chip is a deviation to one bank (relief unit), an attempt to increase the relief efficiency requires a provision of a very large number of relief units and fuse sets within one bank. This leads to an extreme reduction in the area efficiency and an extreme increase in the chip size.
The number of relief units and the number of fuse sets are proportional to the number of banks (relief block units) within the chip. Accordingly, when the number of banks within the chip is increased while maintaining sufficient relief efficiency, it is necessary to increase the number of relief units as well as the number of fuse sets. This leads to a further aggravation in the area efficiency and a further increase in the chip size.
Further, when the number of fuses (fuse sets) becomes larger, this has the following risk. That is, after the semiconductor memory has been tested, there occurs a failure in the accurate disconnection of fuses at the time of disconnecting the fuses by laser in an attempt to register fail addresses for specifying relief units including defective memory cells. This makes it impossible to replace the defective cells with the redundancy circuit. In this case, it is not possible expect any improvement in product yield.
With a view to eliminating the above-described drawbacks, it is an object of the present invention to provide a semiconductor memory having a novel redundancy circuit capable of obtaining high relief efficiency by using a fail address memory (for example, a fuse set) with small memory capacity.
According to one aspect of the present invention, there is provided a semiconductor memory including a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, a mapping spare decoder for relieving the normal decoder, and a mapping memory disposed independent of the mapping spare decoder, and for being recorded with mapping data. The normal decoder is replaced with the fixed spare decoder when a fail address for specifying the normal decoder is registered in the fixed memory. The normal decoder is replaced with the mapping spare decoder when the fail address is registered in the mapping memory and also when the mapping data specifies the mapping spare decoder.
Further, according to another aspect of the invention, there is provided a semiconductor memory including a plurality of banks, and a mapping memory disposed at the outside of the plurality of banks, with no association with a mapping spare decoder, and for being registered with mapping data. Each bank has a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and a mapping spare decoder for relieving the normal decoder. The mapping data has a function of associating the mapping memory with the mapping spare decoder within one of the plurality of banks. Further, when a fail address for selecting the normal decoder within one of the plurality of banks is registered in the mapping memory, the normal decoder is replaced with the mapping spare decoder within one of the banks associated with the mapping memory.
Further, according to still another aspect of the invention, there is provided a semiconductor memory including a plurality of banks, and at least one mapping memory disposed at the outside of the plurality of banks, independent of a mapping spare decoder, and for being registered with mapping data. Each bank has a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and at least one mapping spare decoder for relieving the normal decoder. The at least one mapping memory is associated with the at least one mapping spare decoder based on the mapping data registered in the at least one mapping memory. When the number of the plurality of banks is expressed as 2M (M is a natural number), when the number of the at least one mapping spare decoder is expressed as S1 (S1 is a natural number), and also when the number of the at least one mapping memory is expressed as L, the following relationship is satisfied. 1xe2x89xa7Lxe2x89xa72Mxc3x97S1.
Further, according to still another aspect of the invention, there is provided a semiconductor memory including a plurality of banks, and a mapping memory disposed at the outside of the plurality of banks, with no association with a mapping spare decoder, and for being registered with mapping data. Each bank has a normal decoder, and a mapping spare decoder for relieving the normal decoder. The mapping data has a function of associating the mapping memory with the mapping spare decoder within one of the plurality of banks. Further, when a fail address for selecting the normal decoder within one of the plurality of banks is registered in the mapping memory, the normal decoder is replaced with the mapping spare decoder within one of the banks associated with the mapping memory.
Further, according to still another aspect of the invention, there is provided a semiconductor memory including a plurality of banks, and at least one mapping memory disposed at the outside of the plurality of banks, with no association with a mapping spare decoder, and for being registered with mapping data. Each bank has a normal decoder, and at least one mapping spare decoder for relieving the normal decoder. The at least one mapping memory is associated with the at least one mapping spare decoder based on the mapping data registered in the at least one mapping memory. When the number of the plurality of banks is expressed as 2M (M is a natural number), when the number of the at least one mapping spare decoder is expressed as S1 (S1 is a natural number), and also when the number of the at least one mapping memory is expressed as L, the following relationship is satisfied. 1xe2x89xa7Lxe2x89xa72Mxc3x97S1.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.